1. Field of the Invention
The present invention generally relates to a successive approximation register (SAR) ADC, and more particularly to a successive approximation ADC with capacitance mismatch calibration and method thereof.
2. Description of Related Art
In integrated circuits (IC), capacitance match is always one of the important design considerations. In ICs, such as analog to digital converters (ADCs) and switch-capacitor circuits, the performance of the circuits might be restricted due to capacitance mismatch resulting from deviation in the manufacturing process, such that the circuit cannot achieve the level of the original design.
FIG. 1 illustrates an 8-bit successive approximation register (SAR) analog-to-digital converter (ADC). As shown in FIG. 1, SAR ADC 1 includes two symmetrical digital to analog converters (DACs) 11, 13 which both consist of an array of capacitors (C7 to C0) with binary weighted values. In operation, a comparator 15 first samples and compares the differential input voltages Vip, Vin, and a SAR control logic (“SAR”) 17 switches the switches S7p, S7n to control the terminal voltages on the terminals of the capacitors C7 based on a comparison result of the comparator 15. Due to the change of the terminal voltages, the redistributed charges generate new voltages on the two terminals of the DACs 11, 13. Then, the comparator 15 compares the outputs of the DACs 11, 13 sequentially, and the SAR 17 converts the corresponding digital bits (B1 to B8) based on the comparison result of the comparator 15.
The converted digital bits (Bi) can be used to generate a digital output according to the binary-weighted capacitors (Ci). With reference to the depiction of FIG. 2A, taking the 3-bit successive SAR ADC as an example, under perfect capacitance matching, the values of the binary-weighted capacitors C3-C0 should be 4C, 2C, C, C precisely, respectively. After converting the digital bits B3-B1, the digital output (Dout) can be generated by equation (1).Dout=4*B3+2*B2+B1  (1)
However, due to deviation in the manufacturing process, the capacitance of the capacitor C3 might not equal 4C, as shown in FIG. 2B. Therefore, the digital output calculated with incorrect weighted values of the capacitors is not precise, such that the circuit cannot operate regularly. In order to decrease capacitance mismatch effect, it usually increases the capacitances of the array of capacitors in the circuit, which results in more power consumption and reducing the operating speed of overall SAR ADC.
Therefore, with IC design, a need has arisen to propose a novel circuit which can compensate for or calibrate the capacitance mismatch caused by deviation in the manufacturing process with relatively small capacitance, so as to enable the designed circuit to achieve the original performance and precision.